This invention relates generally to analog-to-digital converters, and in particular to a charge-controlled integrating successive-approximation analog-to-digital converter (ADC).
Conventional successive-approximation ADCs employ a binary search approach to locate each digital bit of a multiple-bit digital word representing an analog voltage value that has been sampled and held to permit the conversion process to take place. The successive-approximation ADC typically includes a comparator to compare predetermined successive binary-weighted reference voltages with the input analog voltage. The successive reference voltages, which are generated by either a parallel-feedback digital-to-analog converter (DAC) or a network of binary-weighted resistive dividers connectable by a controller to D.C. voltage sources, follow the form V.sub.REF =V.sub.RANGE (a.sub.1 2.sup.-1 +a.sub.2 2.sup.-2 +a.sub.3 2.sup.-3 + . . . a.sub.n 2.sup.-n) wherein V.sub.RANGE is the range of the ADC window and each a.sub.n is a digital bit. This type of converter is capable of a moderately fast conversion rate. Some of the disadvantages associated with this type of converter include higher complexity and cost in order to achieve higher accuracy and resolution, and lack of noise rejection without subsequent filtering.
Conventional charge-balanced ADCs operate in a manner similar to successive-approximation ADCs in that capacitors or charge transfer devices are used to manipulate electrical charges in a Q/2.+-.Q/4.+-.Q/8.+-.Q/16, etc., search sequence, adding or subtracting binary-weighted charges to or from a stored charge proportional to an analog voltage, to locate the digital bits. This type of ADC requires the construction of 16 binary ratioed capacitors for a 16-bit ADC. Hence, for 16-bit accuracy, the ADC is a relatively expensive device. Moderate conversion speeds require a high clock frequency, which means these devices consume inordinate amounts of power. This technique has no inherent noise rejection.
Another type of charge-balanced ADC is the dual-slope converter. This converter represents the unknown input voltage as charge stored on a capacitor in an integrator circuit. The amount of charge stored on the integrator capacitor is obtained by measuring the amount of time required to remove the charge. Thus, the time measured is proportional to the unknown voltage. This conversion process has excellent noise immunity achieved by properly setting the time required for the integrator capacitor to acquire charge. The major disadvantage of this type of converter is a long conversion time.
It would be desirable to provide an ADC combining the favorable attributes of successive-approximation and dual-slope converters for high resolution and accuracy, and yet being relatively simple and inexpensive, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility.